`default_nettype none
`timescale 1ns/1ns

module clock(clk);
	output reg clk;

	initial begin
		clk = 0;
	end

	always
//		#10 clk <= ~clk;
		#5 clk <= ~clk;
endmodule

module tb_cons;
	wire clk;
	reg reset;
	wire reset_n = ~reset;
	clock clock(clk);

	initial begin
		reset <= 1;
		#500 reset <= 0;
	end

	initial begin
		$dumpfile("dump.vcd");
		$dumpvars();

		$readmemh("imem.hex", cons.imem);
		$readmemh("dmem.hex", cons.dmem);
		$readmemh("amem.hex", cons.amem);
		$readmemh("mmem.hex", cons.mmem);

		@(negedge reset);
		#20;
	cons.opcclk <= 0;
	cons.nop11 <= 0;
	cons.idebug <= 0;
	cons.sstep <= 0;
	cons.run <= 0;
	cons.errstop <= 0;
	cons.speed <= 0;
	cons.pc <= 1;
		cons.ureset <= 1;
		#500;
		cons.ureset <= 0;
		#1000;
	cons.run <= 1;
		#1000;
//	cons.run <= 0;

		#2000000;
		$finish;
	end

	initial begin : initmem
/*
		integer i;
		for(i = 0; i < 'o20; i = i+1)
			kd11a.m7231_data.r[i] <= i + 'o070700;
		kd11a.m7231_data.r[6] <= 'o2000;
//		kd11a.m7231_data.r['o16] <= 'o4000;

//		for(i = 0; i < 'o20000; i = i+1)
//			memory.mem[i] <= i + 'o102030;
		for(i = 0; i < 'o20000; i = i+1)
			memory.mem[i] <= 0;
		#10;
*/
	end

	cons cons(.clk(clk),
		.reset(reset));

endmodule